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| Radiation Hardened, High Performance Industry Standard Single-Ended Current Mode PWM Controller ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH The ISL7884xASRH is a high performance, radiation hardened drop-in replacement for the popular 28C4x and 18C4x PWM controllers suitable for a wide range of power conversion applications including boost, flyback, and isolated output configurations. Its fast signal propagation and output switching characteristics make this an ideal product for existing and new designs. Features include up to 13.2V operation, low operating current, 90A typ start-up current, adjustable operating frequency to 1MHz, and high peak current drive capability with 50ns rise and fall times. PART NUMBER ISL78840ASRH ISL78841ASRH ISL78843ASRH ISL78845ASRH RISING UVLO 7.0 7.0 8.4V 8.4V MAX. DUTY CYCLE 100% 50% 100% 50% ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH Features * Electrically Screened to DSCC SMD # 5962-07249 * QML Qualified Per MIL-PRF-38535 Requirements * 1A MOSFET Gate Driver * 90A Typ Start-up Current, 125A Max * 35ns Propagation Delay Current Sense to Output * Fast Transient Response with Peak Current Mode Control * 9V to 13.2V Operation * Adjustable Switching Frequency to 1MHz * 50ns Rise and Fall Times with 1nF Output Load * Trimmed Timing Capacitor Discharge Current for Accurate Deadtime/Maximum Duty Cycle Control * 1.5MHz Bandwidth Error Amplifier * Tight Tolerance Voltage Reference Over Line, Load and Temperature * 3% Current Limit Threshold * Pb-Free Available (RoHS Compliant) Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed in the ordering information must be used when ordering. Detailed Electrical Specifications for the ISL788xASRH are contained in SMD 5962-07249. A "hot-link" is provided on our website for downloading. Applications * Current Mode Switching Power Supplies * Isolated Buck and Flyback Regulators * Boost Regulators * Direction and Speed Control in Motors * Control of High Current FET Drivers Pin Configuration ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH (8 LD FLATPACK) TOP VIEW COMP FB CS RTCT 1 2 3 4 8 7 6 5 VREF VDD OUT GND December 21, 2009 FN6991.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH Ordering Information ORDERING NUMBER ISL78840ASRHF/PROTO 5962R0724901QXC 5962R0724901VXC ISL78840ASRHVX/SAMPLE ISL78841ASRHF/PROTO 5962R0724902QXC 5962R0724902VXC ISL78841ASRHVX/SAMPLE ISL78843ASRHF/PROTO 5962R0724903QXC 5962R0724903VXC ISL78843ASRHVX/SAMPLE ISL78845ASRHF/PROTO 5962R0724904QXC 5962R07 24904VXC ISL78845ASRHVX/SAMPLE NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH. For more information on MSL please see techbrief TB363. PART NUMBER ISL78840ASRHF/PROTO (Notes 1, 2) ISL78840ASRHQF (Notes 1, 2) ISL78840ASRHVF (Notes 1, 2) ISL78840ASRHVX/SAMPLE ISL78841ASRHF/PROTO (Notes 1, 2) ISL78841ASRHQF (Notes 1, 2) ISL78841ASRHVF (Notes 1, 2) ISL78841ASRHVX/SAMPLE ISL78843ASRHF/PROTO (Notes 1, 2) ISL78843ASRHQF (Notes 1, 2) ISL78843ASRHVF (Notes 1, 2) ISL78843ASRHVX/SAMPLE ISL78845ASRHF/PROTO (Notes 1, 2) ISL78845ASRHQF (Notes 1, 2) ISL78845ASRHVF (Notes 1, 2) ISL78845ASRHVX/SAMPLE TEMP. RANGE (C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 PACKAGE (Pb-Free) 8 Ld Flatpack 8 Ld Flatpack 8 Ld Flatpack Die 8 Ld Flatpack 8 Ld Flatpack 8 Ld Flatpack Die 8 Ld Flatpack 8 Ld Flatpack 8 Ld Flatpack Die 8 Ld Flatpack 8 Ld Flatpack 8 Ld Flatpack Die 2 FN6991.0 December 21, 2009 Functional Block Diagram ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH VDD START/STOP UV COMPARATOR + + VDD OK ENABLE VREF 5V VREF VREF FAULT + GND 2.5V A A = 0.5 VREF UV COMPARATOR 4.65V 4.80V + - 3 FN6991.0 December 21, 2009 PWM COMPARATOR CS 100mV + + 2R FB + ERROR AMPLIFIER VF TOTAL = 1.15V R T Q OUT SQ 36k RQ VREF 100k 2.9V 1.0V ON 150k OSCILLATOR COMPARATOR <10ns + 8.4mA ON CLOCK RESET DOMINANT 1.1V CLAMP ONLY ISL78841A, ISL78845A Q COMP RTCT Typical Application - 48V Input Dual Output Flyback CR5 +3.3V T1 VIN+ R3 C4 CR4 C17 + C22 + C20 RETURN CR6 R1 36V TO 75V C6 C1 C3 Q1 U2 R16 R17 R19 C14 R18 C21 R21 +1.8V + C15 + C16 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH C2 C5 CR2 C19 4 R28 R4 VINR6 CR1 Q3 VR1 FN6991.0 December 21, 2009 R22 U3 R27 C13 R15 R20 U4 R26 COMP CS FB VREF V DD OUT RTCT GND ISL7884xASRH R10 C12 C8 R13 C11 Typical Application - Boost Converter R8 C10 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH CR1 VIN+ L1 +VOUT + C2 C3 5 Q1 R4 RETURN R9 R5 C9 C1 R1 R2 U1 COMP FB C4 CS RTCT VREF VDD OUT GND R7 VIN+ C8 R6 ISL7884xASRH R3 C5 C7 C6 VINFN6991.0 December 21, 2009 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH Typical Performance Curves 1.01 NORMALIZED FREQUENCY 1.001 1.000 NORMALIZED VREF 0 20 40 60 80 100 120 140 1.00 0.999 0.998 0.997 0.996 0.995 -60 0.99 0.98 -60 -40 -20 -40 -20 TEMPERATURE (C) 0 20 40 60 80 TEMPERATURE (C) 100 120 140 FIGURE 1. FREQUENCY vs TEMPERATURE FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE 1.001 NORMALIZED EA REFERENCE 103 1.000 FREQUENCY (kHz) 100 100pF 220pF 330pF 470pF 0.998 10 1.0nF 2.2nF 3.3nF 4.7nF 6.8nF 0.997 0.996 -60 1 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) 1 10 RT (k) 100 FIGURE 3. EA REFERENCE vs TEMPERATURE FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN Pin Descriptions RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, DMAX, can be approximated from the Equations 1 through 4: t C 0.533 RT CT 0.008 RT - 3.83 t D - RT CT In -------------------------------------------- 0.008 RT - 1.71 (EQ. 1) COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. FB - The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The non-inverting input of the error amplifier is internally tied to a reference voltage. CS - This is the current sense input to the PWM comparator. The range of the input signal is nominally 0V to 1.0V and has an internal offset of 100mV. GND - GND is the power and small signal reference ground for all functions. OUT - This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VDD is below the UVLO threshold. VDD - VDD is the power connection for the device. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f, and the MOSFET gate charge, Qg, (EQ. 2) (EQ. 3) (EQ. 4) f = 1 (tC + tD) D = tC f The formulae have increased error at higher frequencies due to propagation delays. Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given switching frequency for the ISL78841, ISL78845ASRH. The value for the ISL78840, ISL78843ASRH will be twice that shown in Figure 4. 6 FN6991.0 December 21, 2009 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH the average output current can be calculated from Equation 5: I OUT = Qg x f (EQ. 5) Gate Drive The ISL7884xASRH is capable of sourcing and sinking 1A peak current. To limit the peak current through the IC, an optional external resistor may be placed between the totem-pole output of the IC (OUT pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance. TID environment of >50krads requires the use of a bleeder resistor of 10k from OUT pin to GND. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. VREF - The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. The recommended bypass to GND cap is in the range 0.1F to 0.22F. A typical value of 0.15F can be used. Slope Compensation For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. Slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. Adding the external ramp to the current feedback signal is the more popular method. From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation is calculated in Equation 6: 1 Fm = ------------------SnTsw (EQ. 6) Functional Description Features The ISL7884xASRH current mode PWM makes an ideal choice for low-cost flyback and forward topology applications. With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating. Oscillator The ISL7884xASRH has a sawtooth oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (Please refer to Figure 4 for the resistor and capacitance required for a given frequency). Soft-Start Operation Soft-start must be implemented externally. One method, illustrated below, clamps the voltage on COMP. VREF ISL7884xASRH D1 R1 Q1 C1 GND COMP where Sn is the slope of the sawtooth signal and tsw is the duration of the half-cycle. When an external ramp is added, the modulator gain becomes Equation 7: 1 1 Fm = ------------------------------------ = ------------------------( Sn + Se )tsw m c Sntsw (EQ. 7) where Se is slope of the external ramp and becomes Equation 8: Se m c = 1 + ------Sn (EQ. 8) FIGURE 5. SOFT-START The COMP pin is clamped to the voltage on capacitor C1 plus a base-emitter junction by transistor Q1. C1 is charged from VREF through resistor R1 and the base current of Q1. At power-up C1 is fully discharged, COMP is at ~0.7V, and the duty cycle is zero. As C1 charges, the voltage on COMP increases, and the duty cycle increases in proportion to the voltage on C1. When COMP reaches the steady state operating point, the control loop takes over and soft start is complete. C1 continues to charge up to VREF and no longer affects COMP. During power down, diode D1 quickly discharges C1 so that the soft start circuit is properly initialized prior to the next power on sequence. 7 The criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at the switching frequency. The double-pole will be critically damped if the Q-factor is set to 1, over-damped for Q < 1, and under-damped for Q > 1. An under-damped condition may result in current loop instability. 1 Q = ------------------------------------------------ ( m c ( 1 - D ) - 0.5 ) (EQ. 9) FN6991.0 December 21, 2009 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH where D is the percent of on time during a switching cycle. Setting Q = 1 and solving for Se yields Equation 10: 1 1 S e = S n -- + 0.5 ------------ - 1 1 -D (EQ. 10) VREF RTCT signal with the current sense feedback and applies the result to the CS pin as shown in Figure 6. Since Sn and Se are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by tON to obtain the voltage change that occurs during tON. 1 1 V e = V n -- + 0.5 ------------ - 1 1 -D (EQ. 11) ISL78843ASRH R9 R6 CS RTCT C4 where Vn is the change in the current feedback signal (I) during the on time and Ve is the voltage that must be added by the external ramp. For a flyback converter, Vn can be solved for in terms of input voltage, current transducer components, and primary inductance, yielding Equation 12: D T SW V IN R CS 1 1 -V e = --------------------------------------------------- -- + 0.5 ------------ - 1 1 -D Lp V (EQ. 12) FIGURE 6. SLOPE COMPENSATION Assuming the designer has selected values for the RC filter (R6 and C4) placed on the CS pin, the value of R9 required to add the appropriate external ramp can be found by superposition. 2.05D R 6 V e = --------------------------R6 + R9 V (EQ. 16) where RCS is the current sense resistor, fsw is the switching frequency, Lp is the primary inductance, VIN is the minimum input voltage, and D is the maximum duty cycle. The current sense signal at the end of the ON time for CCM operation is Equation 13: ( 1 - D ) VO f N S R CS sw V CS = ------------------------ I O + ------------------------------------------- 2L s NP V (EQ. 13) The factor of 2.05 in Equation 16 arises from the peak amplitude of the sawtooth waveform on RTCT minus a base-emitter junction drop. That voltage multiplied by the maximum duty cycle is the voltage source for the slope compensation. Rearranging to solve for R9 yields Equation 17: ( 2.05D - V e ) R 6 R 9 = --------------------------------------------Ve (EQ. 17) where VCS is the voltage across the current sense resistor, Ls is the secondary winding inductance, and IO is the output current at current limit. Equation 13 assumes the voltage drop across the output rectifier is negligible. Since the peak current limit threshold is 1.00V, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold as shown in Equation 14. V e + V CS = 1 (EQ. 14) The value of RCS determined in Equation 15 must be rescaled so that the current sense signal presented at the CS pin is that predicted by Equation 13. The divider created by R6 and R9 makes this necessary. R6 + R9 R CS = -------------------- R CS R9 (EQ. 18) Example: VIN = 12V VO = 48V Ls = 800H Ns/Np = 10 Lp = 8.0H IO = 200mA Switching Frequency, fsw = 200kHz Duty Cycle, D = 28.6% R6 = 499 Solve for the current sense resistor, RCS, using Equation 15. Substituting Equations 12 and 13 into Equation 14 and solving for RCS yields Equation 15: 1 R CS = ---------------------------------------------------------------------------------------------------------------------------------------------------1 -- + 0.5 N ( 1 - D ) V O f sw D f sw V IN s ------------------------------- ----------------- - 1 + ------ I O + ------------------------------------------- 1-D N Lp 2L s p (EQ. 15) Adding slope compensation is accomplished in the ISL7884xASRH using an external buffer transistor and the RTCT signal. A typical application sums the buffered 8 FN6991.0 December 21, 2009 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH RCS = 295m Determine the amount of voltage, Ve, that must be added to the current feedback signal using Equation 12. Ve = 92.4mV Using Equation 17, solve for the summing resistor, R9, from CT to CS. R9 = 2.67k Determine the new value of RCS (R'CS) using Equation 18. R'CS = 350m Additional slope compensation may be considered for design margin. The above discussion determines the minimum external ramp that is required. The buffer transistor used to create the external ramp from RTCT should have a sufficiently high gain (>200) so as to minimize the required base current. Whatever base current is required reduces the charging current into RTCT and will reduce the oscillator frequency. Fault Conditions A Fault condition occurs if VREF falls below 4.65V. When a Fault is detected OUT is disabled. When VREF exceeds 4.80V, the Fault condition clears, and OUT is enabled. Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors. References [1] Ridley, R., "A New Continuous-Time Model for Current Mode Control", IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991. 9 FN6991.0 December 21, 2009 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH Die Map 10 FN6991.0 December 21, 2009 ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 12/21/09 REVISION FN6991.0 Initial Release CHANGE Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6991.0 December 21, 2009 |
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